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CML Semiconductor Products
PRODUCT INFORMATION
FX631
Features Detects 12kHz and 16kHz SPM Frequencies Low Po Low Power (3.0 VoltMIN <1.0mA) Operation Speechband High Speechband Rejection Proper operties Properties
Low-Voltag w-Volta Low-Voltage SPM Detector
Publication D/631/8 July 1998
one-Follower Pac acket Tone-Follower and Packet Mode Outputs Applications Complex Complex and/or Simple Telephone Systems Call-Charge/-Logging Call-Charge/-Logging Systems
XTAL/CLOCK XTAL/CLOCK OSCILLATOR XTAL
CLOCK OUT
CLOCK IN CLOCK DIVIDERS
SYSTEM
VSS
VDD TONE FOLLOWER OUTPUT SYSTEM
(12kHz/16kHz)
TONE FOLLOWER LOGIC INPUT AMP
12kHz/16kHz
FX631
SIGNAL IN (+) AMP OUT
VBIAS
Fig.1 Functional Block Diagram
Brief Description
The FX631 is a low-power, system-selectable Subscriber Pulse Metering (SPM) detector to indicate the presence, on a telephone line, of both 12kHz and 16kHz telephone call-charge frequencies. Deriving its input directly from the telephone line, input amplitude/sensitivities are component adjustable to the user's national `Must/Must-Not Decode' specifications via an on-chip input amplifier, whilst the 12kHz and 16kHz frequency limits are accurately defined by the use of an external 3.579545MHz telephone-system Xtal or clock-pulse input. The FX631, which demonstrates high 12kHz and 16kHz performance in the presence of both voice and noise, can operate from either a single or differential analogue signal input from which it will produce two individual logic outputs.
1
+
-
SIGNAL IN (-)
32 1
LEVEL DETECTOR DIVIDER
PERIOD MEASURE PACKET MODE OUTPUT PACKET TONE LOGIC
+20dB
SYSTEM
1. Tone Follower Output - A 'tone-following' logic output producing a "Low" level for the period of a correct decode and a "High" level for a bad decode or NOTONE. 2. Packet (Cumulative Tone) Mode Output - To respond and de-respond after a cumulative 40ms of good tone (or NOTONE) in any 48ms period. This process will ignore small fluctuations or fades of a valid frequency input and is available for Processor `Wake-Up', Minimum tone detection, NOTONE indication or transient avoidance. This system (12kHz/16kHz) selectable microcircuit, which may be line-powered, is available in 16-pin plastic DIL and surface mount SOIC and 24-pin plastic SSOP packages.
Pin Number
FX631 FX631 D5 DW/P 1 1
Function
Xtal/Clock: The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in conjunction with the Xtal output (see Figure 2); circuit components are on chip. Using this mode of clock operation, theDescription pin should be connected directly to the Clock In pin. If a clock 2.3 Pin Function Clock Out pulse input is employed to the Clock In pin, this pin must be connected directly to VDD (see Figure XTAL The input of the oscillator inverter. 2). Xtal: The output of the on-chip clock oscillator inverter.
CLKIN The input to the internal clock divider circuitry. When a 3.579545MHz crystal is used, it should be connected across XTAL & XTAL and XTAL Clock Out: A clock signal derived from the on-chip Xtal oscillator. If the on-chip oscillator is should be directly connected to CLKIN. No other external components are necessary because used, this pin should be connnected directly to the Clock In pin. This output should not be used the other oscillator components (capacitor, resistor) are on chip. to clock other devices. When an externally available clock signal is used, it should be inserted at CLKIN. XTAL should be tied to VDD or Vss and XTAL should be left open circuit. XTALN The output of the oscillator inverter
4 5
2 3
6
4
Clock In: The 3.579545MHz clock pulse input to the internal clock-dividers. If a clock pulse SYSTEM A logic Xtal/Clock input (Pin whether the device detects 12Khz SPM tones 2. input is employed, the input pin which controls 1) should be connected to VDD. See Figure(logic 1)
or 16Khz SPM tones (logic 0). It has an internal 1 Mohm pull- up resistor (l 2Khz). NEGIP The negative input, analogue bias circuitry. Held internally gain adjusting POSIP VBIAS: The output of the on-chip positive input and output respectively of theat VDD/2, this pin should amplifier. V (see Figure 2). be decoupled to SS AMPOP External components are used in conjunction with the op -amp according to the required level VSS: Negative supply rail (GND). whether the incoming signal is differential or common mode. sensitivity and depending on
8
7
12 13 17 18 19
8 9 10 11 13
VDD The power supply, negative signal inputs to, and the output from, the input gain The positive and ground and filter bias pins respectively. Signal In (+): VSS adjusting signal amplifier. Refer to the graph in Figure 4 for guidance on BIASsetting level sensitivities be national specifications, and the selection of gain Voo and bias should each to de- coupled, via a 1 .0@F capacitor, to VSS. Signal In (-): adjusting components.
Amp Out:
TTFOP TRUE TONE FOLLOWER OUTPUT. This is the pin that responds and deresponds within 4ms of a good tone appearing or disappearing.
It is thus Output: This of the provides Tone Followerlike an envelopeoutput SPM tone.a logic "0" (Low) for the period of a detected tone, and a logic "1" (High) for NOTONE detection. See Figure 7. * logic 0 represents `detect' and logic 1 represents `not detect'.
20
14
DTFOP This logic output that `delayed tone follower' a cumulation of 40ms of 'good' Packet Mode Output: A is the output of the will be available after block. tone has been received. This packet mode tone follower will only respond when a tone It will respond when 40ms of good tone has been sufficient time, i.e. a cumulation of 48ms in frequency of sufficient quality has been received for received within any 48ms window. The 40ms is divided into 24 `packets' of breaks will be ignored. This output of 2.667ms each (12Khz any 48ms, short tone bursts or 2ms each (16Khz mode) or 15 `packets'provides a logic "0" (Low) for mode). Each packet represents 32 cycles of SPM frequency. The window a detected tone and a logic "1" (High) for NOTONE detection. See Figure 7. is a shifting window, ie. the 48ms window is assessed every 2ms (16Khz mode) or 2.667ms (12Khz). If the necessary number of good packets are consecutive, the output will respond in the minimum time of 40ms.
21
15
System: The logic input to select device operation to either 12kHz (logic "1" - High) or 16kHz (logic "0" - Low) SPM systems. This input has an internal 1M pullup resistor (12kHz). * logic 0 represents `detect' and logic 1 represents `not detect'.
24
16
VDD: Positive supply rail. A single, stable power supply is required. Critical levels and voltages within the FX631 are dependant upon this supply. This pin should be decoupled to VSS by a capacitor mounted close to the pin. Note that if this device is `line' powered, the resulting supply must be stable. See notes on Microcircuit Protection from high and spurious line voltages.
2, 3, 7, 5, 6, 12 9, 10, 11, 14, 15, 16, 22, 23
No internal connection, leave open circuit.
2
Information Application Information
External Components
VDD C1
XTAL/CLOCK
XTAL/CLOCK X1 XTAL CLOCK OUT
1 2 3 4 5 6
16 15 14
VDD SYSTEM
VSS
For use with a Clock Pulse input - Remove Xtal (X1) - Connect Pin 1 to VDD - Remove link (Pins 3/4) - Input clock pulses to CLOCK IN
PACKET MODE OUTPUT
CLOCK IN
CLOCK IN
FX631DW
13 12 11 10
TONE FOLLOWER OUTPUT
AMP OUT SIGNAL IN (-)
R1 C3 R2 R3 C4
VBIAS VSS
7 8
SIGNAL IN (+)
9
R4
C2 VSS
Fig.2 Recommended External Components - Differential Input Mode
Component R1 R2 R3 R4 C1 C2 C3 C4 X1
Value RFEEDBACK RIN (-) RIN (+) RBIAS 1.0F 20% 1.0F 20% CIN (-) CIN (+) 3.579545MHz
External Components 1. The values of the Input Amp gain components illustrated are calculated using the Input Gain Calculation Graphs (Figures 4 and 5). Whilst calculating input gain components, for correct operation, it is recommended that the values of resistors R1 and R4 are always greater than, or equal to, 33k.
2. Refer to following pages for advice on Microcircuit Protection from high and spurious line voltages.
Differential Input
Common Mode Input
INPUT AMP
INPUT AMP
Ring (b)
VBIAS
VBIAS
VSS
VSS
Fig.3 Example Input Configurations
3
+
-
+
-
Tip (a)
Information Application Information ......
-10 -15
775mVrms
-20 MUST DECODE LEVEL -25 -30 -35 -40 -45 MINIMUM AMPLIFIER GAIN -50 -25 -20 -15 -10 -5 MAXIMUM AMPLIFIER GAIN 0 5 10 15 20 25 AMPLIFIER GAIN (dB) o o VDD = 3.3 (+/- 0.1) VOLTS TEMP = -40 C to +85 C MUST NOT DECODE LEVEL
Fig.4 Input Gain Calculation Graph for VDD = 3.3V
SIGNAL LEVEL (dB)
0dB ref:
o
o
Fig.5 Input Gain Calculation Graph for VDD = 5.0V
4
Information Application Information ......
Input Gain Calculation
The input amplifier, with its external circuitry, is provided on-chip to set the sensitivity of the FX631 to conform to the user's national level specification with regard to `Must' and `Must-Not' decode signal levels. With reference to the graphs in Figures 4 and 5, the following steps will assist in the determination of the required gain/attenuation. Step 1 Draw two horizontal lines from the Y-axis (Signal Levels (dB)). The upper line will represent the required `Must' decode level. The lower line will represent the required `MustNot' decode level. Step 2 Mark the intersection of the upper horizontal line and the upper sloping line; drop a vertical line from this point to the X-axis (Amplifier Gain (dB)). The point where the vertical line meets the X-axis will indicate the MINIMUM Input Amp gain required for reliable decoding of valid signals. Step 3 Mark the intersection of the lower horizontal line and the lower sloping line; drop a vertical line from this point to the X-axis. The point where the vertical line meets the X-axis will indicate the MAXIMUM allowable Input Amp gain. Input signals at or below the `Must-Not' decode level will not be detected as long as the amplifier gain is no higher than this level. Select the gain components as described opposite.
Input Gain Components
With reference to the gain components shown in Figures 2 and 3. The user should calculate and select external components (R1, R2/C3, R3/C4, R4) to provide an amplifier gain within the limits obtained in Steps 2 and 3. Component tolerances should not move the gain-figure outside these limits. It is recommended that the designed gain is near the centre of the calculated range. The graphs in Figures 4 and 5 are for the calculation of input gain components for an FX631 using a VDD of 3.3 (0.1) or 5.0 (0.5) volts respectively. Use this area to keep a permanent record of your calculated gains and components
Implementation Notes
Aliasing Due to the switched-capacitor filters employed in the FX631, care should be taken, with the chosen external components, to avoid the effects of alias distortion. Possible Alias Frequencies: 12kHz Mode = 52kHz 16kHz Mode = 69kHz If these alias frequencies are liable to cause problems and/or interference, it is recommended that anti-alias capacitors are employed across input resistors R1 and R4. Values of anti-alias capacitors should be chosen so as to provide a highpass cutoff frequency, in conjunction with R1 (R4) of approximately 20kHz to 25kHz (12kHz system) or 25kHz to 30kHz (16kHz system). i.e. C = 1 2 x x f0 x R1 When anti-alias capacitors are used, allowance must be made for reduced gain at the SPM frequency (12kHz or 16kHz).
5
Microcircuit Protection Telephone systems may have high d.c. and a.c. voltages present on the line. If the FX631 is part of a host equipment that has its own signal input protection circuitry, there will be no need for further protection as long as the voltage on any pin is limited to within VDD + 0.3V and VSS -0.3V. If the host system does not have input protection, or there are signals present outside the device's specified limits, the FX631 will require protection diodes at its signal inputs (+ and -). The breakdown voltage of capacitors and the peak inverse voltage of the diodes must be sufficient to withstand the sum of the d.c. voltages plus all expected signal peaks. Clock Out The Clock Out pin is intended to drive the FX631 Clock In pin only. It is not recommended that it be used to clock other devices within the host equipment.
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3 to 7.0V Input voltage at any pin (ref VSS = 0V) -0.3 to (VDD + 0.3V) Sink/source current (supply pins) +/- 30mA (other pins) +/- 20mA Total device dissipation (DW/P) @ TAMB 25C 800mW Max. (D5) @ TAMB 25C 550mW Max. Derating (DW/P) 10mW/C (D5) 9mW/C -40C to +85C Operating Temperature (TOP): FX631DW/D5/P Storage temperature range (TST): FX631DW/D5/P -40C to +85C Min. Max. Unit Functional Limits ...... Supply Voltage (VDD) 3.0 5.5 V at 25C All device characteristics are measured under the following conditions unless otherwise specified: VDD = 3.3V to 5.0V TOP = -40 to +85 C. Audio Level 0dB ref: = 775mVrms. Noise Bandwidth = 50kHz. Xtal/Clock or `Clock In' Frequency = 3.579545MHz. 12kHz or 16kHz System Setting.
Characteristics
Supply Current
See Note
1 2
Min.
70 90 3.558918 100 100 60.0 0.7 10.0 11.820 12.480 15.760 16.640 7.8 22.0 -36.0 -25.0 40.0
Typ.
- 100 1.0 14.0
Max.
1.1 2.2 30 10 3.589368 3.8 30.0 12.180 11.520 16.240 15.360 15.5 -29.0 10.0 48.0
Unit
mA mA %VDD %VDD %VDD %VDD MHz ns ns dB Hz M M M k kHz kHz kHz kHz kHz kHz mVp-p dB dB dB ms ms Notes .. .. .. .. ..
Input Logic "1" (High) Input Logic "0" (Low) Output Logic "1" (High) Output Logic "0" (Low) Xtal/Clock or Clock In Frequency "High" External Clock Pulse Width "Low" External Clock Pulse Width Input Amp D.C. Gain Bandwidth (-3dB) Input Impedance Logic Impedances Input (System) (Clock In) Output Overall Performance 12kHz Detect Bandwidth 3 12kHz Not-Detect Frequencies (below 12kHz) 3 12kHz Not-Detect Frequencies (above 12kHz) 3 16kHz Detect Bandwidth 3 16kHz Not-Detect Frequencies (below 16kHz) 3 16kHz Not-Detect Frequencies (above 16kHz) 3 Sensitivity 1, 4 Tone Operation Characteristics Signal-to-Noise Requirements (Amp Input) 5, 6, 7, 8 Signal-to-Voice Requirements (Amp Input) 5, 6, 7, 9 Signal-to-Voice Requirements (Amp Output) 7, 8 Tone Follower Output Response and De-Response Times Packet Mode Output Response and De-Response Times 3, 10 3, 10
10.0 20.0 -40.0 -
6
Specification ......
Notes 1. 2. 3. 4. 5. 6. 7. 8. VDD = 3.3V VDD = 5.0V With adherence to Signal-to-Voice and Signal-to Noise specifications. With Input Amp gain setting: 15.5dBMIN/18.0dBMAX. Common Mode SPM and balanced voice signal. Immune to false responses. Immune to false de-responses With SPM and voice signal amplitudes balanced; To avoid false de-responses due to saturation, the peak-to-peak voice+noise level at the output of the Input Amp (12/16kHz Filter Input) should be no greater than the dynamic range of the device. Maximum voice frequencies = 3.4kHz Response, De-Response and Power-up Response Timing.
9. 10.
Information Application Information ......
12.00kHz
11.52kHz 11.82kHz 12.18kHz 12.48kHz
16.00kHz
15.36kHz 15.76kHz 16.24kHz 16.64kHz
WILL-NOT DECODE FREQUENCIES
WILL-NOT DECODE FREQUENCIES
WILL-NOT DECODE FREQUENCIES
WILL-NOT DECODE FREQUENCIES
FREQUENCIES
F0 - 4%
F0 - 1.5%
F0
F0 + 1.5%
F0 + 4%
F0 - 4%
F0 - 1.5%
FREQUENCIES
F0 + 1.5%
WILL-DECODE
WILL-DECODE
F0
F0 + 4%
Fig.6 Will/Will-Not Decode Frequencies
System Timing
SIGNAL INPUT
TONE NOTONE
TONE FOLLOWER OUTPUT
PACKET MODE OUTPUT
RESPONSE DELAY
SIGNAL INPUT ......
TONE FOLLOWER OUTPUT ......
DERESPONSE DELAY
PACKET MODE OUTPUT ......
Fig.7 Examples of Input and Output Relationships
7
Package Outlines
The FX631 is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top.
Handling Precautions
The FX631 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage.
FX631DW 16-pin plastic S.O.I.C.
(D4)
FX631D5
24-pin plastic S.S.O.P.
NOT TO SCALE
NOT TO SCALE
Max. Body Length Max. Body Width
10.49mm 7.59mm
Max. Body Length Max. Body Width
8.33mm 5.38mm
FX631P
16-pin plastic DIL
(P3)
NOT TO SCALE
Ordering Information Ordering Information
FX631DW FX631D5 FX631P 16-pin plastic S.O.I.C. 24-pin plastic S.S.O.P. 16-pin plastic DIL (P3)
Max. Body Length Max. Body Width 20.57mm 6.60mm
(D4)
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.
8
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/1 February 2002

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